The present invention is directed to fabricating integrated circuits on a semiconductor wafer and, more particularly, to methods and systems for optimizing the number of dies that can be produced on a particular wafer.
In semiconductor design and manufacturing, it is desirable to optimize the number of dies that can fit in a wafer of a particular size or diameter. The number of dies in a wafer is often referred to in the art as dies per wafer (DPW). For any particular wafer diameter [d, mm] and target die size [S, mm2], the number of dies that can be sliced out of the wafer can be estimated by the following expression:
      D    ⁢                  ⁢    P    ⁢                  ⁢    W    =      d    ⁢                  ⁢          π      ⁡              (                              d                          4              ⁢              S                                -                      1                                          2                ⁢                S                                                    )            
Electronic Design Automation (EDA) software refers to a category of software tools used for designing electronic systems such as integrated circuits. It would be desirable if EDA software could optimize the number of dies that can be produced or fabricated in a particular wafer.